Hello everyone, the blogger has been busy for a few days recently, no updates, and officially returned today. Then it's time for daily learning again. Today, let's talk about the power-on reset of FPGA. Welcome to exchange learning together.
In FPGA design based on verilog, we can often see the following forms of progress:
The signal rst_n is used to initialize the variables used in the process. This reset signal is very important. If there is no reset, the initial values ​​of some registers will become unknown. If the FPGA starts working at this time, it is easy to cause errors.
So, where does this reset signal come from? Do we have to manually press the reset button every time we power on the system?
the answer is negative! This reset signal is actually generated by a specific program. Every time the system is powered on, a reset signal is generated by the program, thus avoiding manual reset.
I found a variety of solutions on the Internet, and I think that only this program is relatively simple and practical.
Description:
1. The first process is used for delay. When power is turned on, the delay is 100ms to ensure that the FPGA reaches a stable state; at this time, sys_rst_n is always 0, that is, the system clock is in the reset state;
2. When the 100ms delay ends, sys_rst_n is released synchronously with the system clock, that is, sys_rst_n is pulled high, the reset ends, and the system begins to work normally.
Chat here today, everyone, come on.
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