Designers who choose FPGA devices with excellent debug capabilities can shorten development cycles and reduce costs while significantly speeding time to market. FPGA and SoC designers have to overcome many challenges before they can put their products into production.
In general, they first need to evaluate the right device for their design; then, use hardware description language (HDL) design, place and route devices, and finally, debug the entire FPGA before putting it into production.
For many designs, especially in the industrial and embedded markets, there are countless FPGAs to choose from. In most cases, deciding which FPGA vendor to choose depends on its associated software development experience. While software development experience should also be a consideration, the more important factors should be debugging capabilities and support for accelerated production. Currently, Altera, LatTIce, Microsemi, and Xilinx offer many FPGA debug tools, but designers evaluate future FPGA design strategies. You should consider a smarter debugging tool.
Basic Debugging – Logic AnalyzerA logic analyzer is available as a debugging tool for every major FPGA vendor. This is a technique that uses internal FPGA logic cells and embedded block memory to implement functions. Designers can specify which signals to monitor and set up triggers to tell the logic analyzer when to start collecting data. Once the logic analyzer is set up, the designer must run the synthesis and place and route again in sequence to incorporate functionality into the design. Once the design is recompiled and reprogrammed, the designer can begin to observe the logic signals acquired by the logic analyzer.
It should be noted that since these signals require sampling, they do not collect real-time performance of the data. The logic analyzer can only run at a rate that allows it to acquire data and store the data in internal memory. Since the design must be recompiled to insert the logic analyzer, this process may actually eliminate the vulnerability being sought. Although this may seem good, it doesn't know what the original problem is, meaning that when the compositing and place-and-route operations are performed later, the problem may reappear and reappear.
Still, designers can see the signal state based on trigger conditions, which does help debug design problems. Using a logic analyzer is an iterative process. The designer looks for problems, updates them, then recompiles the design, reviews the new results, and repeats the process until a vulnerability is discovered. Each iteration and processing each specific vulnerability takes a different amount of time, and because of the sampling speed of the logic analyzer, not all problems can be found.
Next generation debugging toolsDue to the limitations of logic analyzers, the industry has designed a new generation of debugging tools to accelerate FPGA and board verification. Some EDA vendors integrate logic analyzer functionality into the synthesis tool, reducing the time it takes for the vulnerability to find iterations, viewing the design and making trigger setup easier. Designers can also change the design to automatically map back to the register transfer level (RTL) code. To save internal FPGA resources, some EDA tools can acquire multiple sets of signals and multiplex them. This is helpful when we don't know the actual source of the problem at the beginning of the debugging process. Synopsys has implemented these features in its idenTIfy logic analyzer and Synplify synthesis tool. Although they provide these improvements for the debugging process, these methods are limited because they require recompilation, which affects the original design and slows signal acquisition.
In fact, it is helpful for engineers, in addition to logic analyzers, and oscilloscopes. This feature allows real-time display of device internal signals. It is also ideal to use the probe to detect nodes in the FPGA in real time, forcibly assign different values ​​to the internal signals, and observe the immediate impact on the design. In addition, the ability to detect internal memory and SERDES transceiver probe points are also very useful. Providing all of these capabilities without affecting the FPGA design will significantly simplify the debugging process.
An example of this approach is the SmartDebug toolbox in the Microsemisystems Libero SoC software, which is used with the company's SmartFusion2, IGLOO2 and RTG4 FPGAs. This toolkit enables designers to debug FPGA structures, memory blocks, and SERDES as if they were using an oscilloscope. With this intelligent debugging, you can take advantage of dedicated probe points built into the FPGA fabric to significantly speed up and simplify the debugging process. Different probe points can be selected without recompiling the design. Enhanced debug features provide access to any logic component, allowing designers to check input and output status in real time without affecting the user's FPGA design. These features include:
- Field probe: Allows the use of two dedicated probes configured to observe the probe points of any input or output in the logic element (Figure 1). The probe data can then be sent to the oscilloscope or even rebooted back into the FPGA fabric to drive the internal logic analyzer. These probe points are dynamic in real time. Probe points can be changed on the fly via software without recompiling or reprogramming the FPGA.
- Active probe: This feature allows dynamic asynchronous read or write of triggers or probe points. This ability allows the user to quickly observe the logic output internally or by writing probe points to quickly influence how the experimental logic will be affected. Any number of signals can be forced to a specified value, just like a live probe, without the need to recompile or reprogram the FPGA.
Probe Insertion: This is used to insert additional probes into the design and output signals to the FPGA package pins for evaluation and debugging of the design. This feature does require additional placement and routing to add signals to the I/O, but does not necessarily require full recompilation.
Figure 1 Example of field probe use (Source: Microsemi)
FPGA designers spend 30% or more of their time on debugging. Depending on the size and status of the project, even more debugging time is required. Because debugging involves many iterations, observability and controllability are limited, and layout and routing, timing closure, and reprogramming are often re-run, so debugging is a painful task. Smart debug tools enable engineers to validate their FPGA designs faster than just using traditional plug-in logic analyzers. These tools allow designers to observe signal and control signal status in real time throughout the design, significantly improving debugging speed.
Recently, according to a customer report, they spent a week trying to debug a problem with an internal logic analyzer. But after replacing it with a smart debugging tool, the engineer found the problem in just two hours. Eventually, this problem came from a completely different design module that was observed when engineers used logic analyzers. Engineers then used active probe features to force different values ​​and ensure that the circuit responded appropriately, further improving the design.
For FPGA designers, enhanced debugging capabilities are significant. The latest solutions significantly reduce debug verification time and provide unparalleled visibility and control for FPGAs. As a result, designers who pay more attention to FPGA debugging capabilities when selecting devices can shorten development cycles, reduce costs, and significantly speed up time to market.
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