In the introduction of the previous article, you have some understanding of the use of ila core. When doing pure logic design, add the ILA core and define it in the code. But FPGA is more than just pure logic. When you implement a project at the embedded level, you will use soft cores, and then you will use canvas. As shown in the figure below, Microblaze is a processor. You can see that each module is an IP core. We cannot modify the code. What if we want to check the port of a module? Can't define an ILA core in the code!
In fact, it is very simple here. You can add an ILA core directly on the canvas, and then connect the desired signal line. You don't need to define this ILA core in the code. But doing this means that you have not been able to use Xilinx's online debugging tools flexibly, because there is an easier way haha.
As shown in the figure below, for this IP core, its output is axi_stream. What should we do if we want to check its working timing?
First of all, we select his signal line, right-click, you can see an option "Mark Debug", and a green beetle will appear after selecting it, which means that all the signals of axi_stream have been introduced into the ILA.
If we don't want to add this debug signal, just right-click and there will be an "Unmark Debug" option, which will be canceled when you click it.
Then click Save in Vivado, which completes the addition of the debug signal, isn't it very convenient.
Let’s digest this method slowly, and then I will introduce another debugging method to you, hehe.
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