We will carry out research and development of 3G TD-SCDMA communication equipment with the cooperation of the Ministry of Information Industry, the Institute of Telecommunications Science and Technology, Chongqing University of Posts and Telecommunications, Chongqing Mobile Communication Engineering Research Center, China Post, and the company to ensure the development of a full set of 3D TD-SCDMA communication equipment in the near future. TD-SCDMA system equipment, and put into trial and operation. One of the important features of the 3G system is the increased data rate.
In the terminal design of the TD-SCDMA system, only the processing rate of the analog baseband part is: 1.28 & TImes; 12 & TImes; 4 & TImes; 2 (= 122.88 Mb / s, ADC, DAC design is 12-bit precision, 4 times oversampling), which has entered High-speed data rate field. With the development of technology, the digital system data rate, clock rate and circuit density are increasing. The new serial data communication standard has pushed the data to the order of Gb/s, and the rise time reaches sub-nanoseconds, cable, mutual Connections, printed boards, and silicon will exhibit distinct behaviors from low-speed designs, with signal integrity issues that make high-speed digital system design a serious challenge. Therefore, signal integrity issues must be addressed and addressed in the development and high-speed design of third-generation mobile communication devices.
Signal integrity problem
1. Definition of signal integrity
Signal Integrity is a state in which the signal is not damaged. It indicates that the signal maintains its correct functional characteristics after transmission through the signal line. The signal can respond with the correct timing and voltage in the circuit. It can be known from the timing of the IC if the signal is in steady state time (in order to correctly identify and process the data, The IC requires a large transition within the time period during which the input data remains unchanged before and after the clock edge, and the IC may misjudge or lose part of the data. If the signal has good signal integrity, the circuit has the correct timing relationship and signal amplitude, and the data will not be captured by mistake, which means that the receiver can obtain relatively pure data. Conversely, if a signal integrity fault such as false triggering, damped oscillation, overshoot, undershoot occurs, any signal transition will occur, causing the input distortion data to be sent into the latch or captured on the distorted clock edge. Data, the signal can not respond properly, resulting in abnormal system operation and performance degradation. Figure 2 shows the simulation results for signal integrity.
2. The cause and performance of signal integrity
Signal integrity stems from the interconnection of circuits such as wires, substrates, and wells. Since a length of wire is not just an electronic conductor, it is resistive in the low frequency band, capacitive in the middle frequency band, inductive in the high frequency band, and becomes a radiating antenna when it is very high frequency. It is this antenna effect that leads to signal crosstalk and electromagnetic interference (EMI). Since the interaction of carriers in the conductor with atoms and grains produces electrical resistance, as the characteristic size is compressed to less than 0.5 μm, the skin effect causes the metal surface resistance to decrease more slowly than the section resistance, resulting in signal integrity damage. The capacitive effect due to the structure with too close independent voltage increases as the wiring pitch decreases, which has a greater potential impact on the transmission characteristics of the signal. The inductive effect, determined by lead size and return path, is a major concern for package and board design. When the IC size is less than 0.5 μm, the inductance effect becomes very noticeable. There will be significant mutual inductance between the two parallel traces, and some noise will be coupled into the logic circuit, causing the signal to exhibit a completely different phenomenon from the low frequency design. The ability of digital systems to tolerate signal integrity problems is limited. To a certain degree of signal integrity problems, system performance may be degraded or not at all. Simulation results confirm that the IC switching speed is too high, the layout of the termination components is inadequate, and the interconnection of the circuit is unreasonable, which will cause signal integrity problems. Signal integrity mainly includes reflection, crosstalk, oscillation, ground bounce, and so on.
Signal reflection
Signal reflection (reflecTIon) is the echo on the transmission line. A portion of the signal power is transmitted to the load via the transmission line and the other portion is reflected to the source. In high-speed design, the conductor can be equivalent to a transmission line instead of a conductor in a lumped parameter circuit, and its transmission effect can be studied by examining its impedance at different frequencies. If the edge rate is as high as 1V/ns (ie, dV/dt), a wire shorter than 0.5 inch can be used to build a T-type concentrating parameter RLC (or RC, LC) model, and multiple T-type cascades are combined into longer Transmission line. In order to reduce the amount of computation of the simulation, a continuous transmission line model can also be established. If the impedance is matched (source impedance, transmission line impedance, and load impedance are equal), reflection will not occur. Conversely, if the load impedance is mismatched with the transmission line impedance, it will cause the end reflection. Signal geometry, improper termination, transmission through the connector, and discontinuity of the power plane can cause signal reflections.
Signal overshoot and undershoot
Signal overshoot refers to the first peak (or valley) of a signal transition exceeding a specified value - the highest voltage for a rising edge and the lowest voltage for a falling edge. Undershoot refers to the next valley (or peak) of a signal transition. Signal overshoot and undershoot are caused by excessive IC switching rate and reflection of signal transmission path. Multiple reflections between the driver and the receiver will form a damped oscillation. If the oscillation amplitude exceeds the input switching threshold of the IC, the clock will be wrong. Or the wrong reception of data, excessive overshoot may also cause overvoltage or even damage to components inside the IC.
Signal crosstalk
Cross-talk is an electromagnetic coupling phenomenon between an induced voltage and an induced current between signal lines that are not electrically connected. This coupling causes the signal line to act as an antenna, its capacitive coupling induces a coupling current, inductive coupling induces a coupling voltage, and increases with increasing clock speed (resulting in increased edge rate) and reduced design size. Big. This is because when the alternating signal current on the signal line passes, an alternating magnetic field is generated, and other signal lines in the magnetic field induce a signal voltage. In the low frequency band, the coupling between the wires can be established as a coupling capacitance model, and in the high frequency band, it can be established as an LC centralized parameter wire or transmission line model. PCB board layer parameters, signal line spacing, electrical characteristics of the driver and receiver terminals, and signal line termination methods all have a certain impact on crosstalk.
Electromagnetic interference
Electromagnetic interference is similar to signal crosstalk. Signal crosstalk is the coupling between two transmission lines that occur on a PCB. The electromagnetic interference is caused by interference from a radiation source outside the PCB (such as a test probe or other PCB board). EMI modeling can treat wire segments as dipole antennas.
Signal oscillation and surround
Signal ringing and rounding are manifested by repeated overshoot and undershoot of the signal, shaking up and down the threshold of the logic level, the oscillation is underdamped, and the surround is overdamped. The oscillation and surrounding of the signal is mainly caused by excessive parasitic inductance and capacitance on the transmission line, causing the terminal impedance to be mismatched with the source. As with reflection, they can be suppressed by proper termination. Generally, the periodic pulse signal contains a wealth of higher harmonics and is prone to signal integrity failures, such as clock signals, and should be guarded against.
Signal delay
Signal delay indicates that the data or clock signal did not reach the end of the line for a certain amount of time and amplitude within a specified time. The IC can only receive data at a specified timing, and excessive signal delay can cause timing violations and functional clutter. Signal delay is caused by the transmission line effect that drives the overload and the trace is too long. The equivalent capacitance and inductance on the transmission line will delay the digital switching of the signal, affecting the setup time and hold time of the IC. If the delay is too large, the IC will not be able to correctly judge the data.
Ground bounce and substrate coupling
Ground bounce, referred to as ground bounce, refers to the phenomenon that a large amount of noise is generated between the power source and the ground plane due to the large current surge in the circuit. If a large number of chips are switched synchronously, a large transient current will flow from the chip to the power plane. The parasitic inductance, capacitance and resistance between the chip package and the power supply will cause power supply noise, resulting in a large potential plane. Voltage fluctuations (possibly up to 2v) are sufficient to cause malfunctions of other components. Due to the division of the ground plane (digital ground, analog ground, shielded ground, etc.), it may cause the digital signal to rebound to the ground plane when it goes to the analog ground area. The same power plane split, the same hazard may occur. An increase in load capacitance, a decrease in resistivity, an increase in parasitic parameters, an increase in switching rate, and an increase in the number of synchronous switchings may result in an increase in ground bounce.
At the same time, underlay coupling may make the design more challenging. In silicon design, since the substrate and well have a finite resistivity, a certain voltage drop occurs when a current flows therethrough. The threshold voltage (on) of the MOSFET depends on the effective voltage of the substrate (or well) under the gate, which means that any substrate current can not only cross the threshold voltage of the MOSFET, but also cross the logic gate or clock circuit. The threshold voltage makes the design very unreliable. As the horizontal and vertical dimensions decrease, the resistance of the substrate and well layers increases and the situation becomes worse.
Signal integrity solution
For chip design, there are usually two ways to solve signal integrity problems. The RF solution focuses on the transmission line, often using impedance matching on the package boundary, while the digital (ie, broadband) solution emphasizes the choice of package, controlling the number of simultaneous switching and switching speed, and using between the external power supply pins of the package and ground. Bypass capacitors, the capacitance inside the IC is achieved by the overlap of the metal layers, which provides a local low-impedance path for high-speed transient currents to prevent ground bounce.
However, when faced with signal integrity issues in deep sub-micron designs, the usual solution no longer applies. For example, limiting the edge rate (Slew rate) can significantly improve ground bounce and crosstalk, but it also limits the clock rate. Researching new solutions must be able to accommodate deep submicron IC designs. For example, increasing substrate resistance can be solved by silicon-on-insulator (SOI), a technology widely used in micro-IC designs. Now, the main methods to solve the signal integrity problem are circuit design, reasonable layout and modeling and simulation.
1, circuit design
In the circuit design process, the number of outputs is synchronously controlled by design control, and the maximum edge rate (dI/dt and dV/dt) of each unit is controlled to obtain the lowest and acceptable edge rate, which can effectively control signal integrity. . Differential signals can also be selected for high output function blocks such as clock drivers. For example, the clock typically uses an ECL signal or a full swing differential signal. For application engineers, passive components (resistors, capacitors, and ferrites) are typically terminated on the transmission line to achieve impedance matching between the transmission line and the load. The choice of termination strategy should be a compromise between increasing component count, switching speed, and power consumption. Terminating the series resistor R or RC circuit should be as close as possible to the excitation or receiver, and obtain impedance matching. At the same time, the resistor R (such as 10Ω) can consume the useless DC power of the logic circuit. The capacitor (such as 39PF) can meet the switch. The damping oscillation strength is weakened under the condition of speed, but at the same time, the capacitor must be carefully selected to prevent ringing caused by its lead inductance.
2, reasonable wiring
Wiring is very important. Designers should use existing design experience, integrate multiple possible solutions, optimize wiring, and eliminate potential problems without violating general principles. While there are some rule-driven routers that help designers optimize their designs, there is no router that is completely customizable by the user and fully supports signal integrity analysis. The routing tool should be combined with all parasitic extraction to obtain accurate predictions of time lag and latency. Successful routers should not only have accurate parasitic extraction, but also be combined with signal integrity tools to cut wires and reroute when signal integrity is found to fall below the required threshold.
3, modeling and simulation
Properly performing circuit modeling and simulation is the most common solution. In modern high-speed circuit design, simulation analysis shows its superiority. It gives the designer accurate and intuitive design results, which facilitates early detection of hidden dangers, timely modification, shortened design time and reduced design cost. The designer should make reasonable estimates of relevant factors and establish a reasonable model. For IC design, the simulation of the circuit must be carried out in a packaged environment, and the simulation results can be closer to the silicon test results returned after the mold is molded. Since signal integrity issues often occur as intermittent errors, emphasis is placed on synchronous switching control, simulation, and packaging to ensure that the design meets signal integrity requirements and solves problems before wafer fabrication. For IC applications, simulation can be used to select reasonable termination components and optimize the layout of components, making it easier to identify potential problems and timely adopt correct termination strategies and layout constraints to resolve related signal integrity issues. As clock frequencies increase and IC size continues to decrease, maintaining signal integrity is becoming more challenging for designers, making modeling and simulation an integral part of the design.
Introduction to Signal Integrity Simulation Models and Tools
There are many simulation tools for analyzing signal integrity, each with its own characteristics.
1 SPICE model
The SPICE (Simulation Program with Integrated Circuit Emphasis) model was first developed and has become an informal standard for analog transistor circuit description in the IC industry. It is based on transistor and diode characteristic parameters modeling, so the amount of computation is very large, the operation is extremely time consuming (may be several days), so users need to make a compromise between simulation accuracy and computational time. The SPICE model generally does not support the simulation of coupled lines (or loss lines), which is a key factor in signal integrity simulation in high speed circuit design.
2 IBIS model
The IBIS (Input/Output Buffer Information Specification) model is an international standard that reflects the electrical characteristics of the chip drive and reception. Based on the V/I curve, it quickly models the I/O BUFFER. It provides a standard file format to record parameters such as excitation source output impedance, rise/fall time, and input load. It is ideal for oscillation and crosstalk. System level calculation and simulation of frequency effects. IBIS is a simple model with small calculations, fast speed and high precision. It has been widely used.
3 VHDL-AMS
VHDL-AMS is a modeling language for analog and mixed-signal behavior that uses analog equations and digital VHDL to describe circuit functions. It is a relatively new standard, has no extensive model developer base, and is not supported by many simulators. Much of the work of the model simulation developer needs to be done before it is widely used for signal integrity simulation.
4 Quantic EMC
Quantic EMC is a signal integrity and EMC software simulation analysis tool. It is a dedicated EMC analysis tool for Siemens. Its Omega PLUS is software that Quantic EMC runs on a PC. It uses the VI model of the device to easily simulate signal integrity and EMI, which is powerful and efficient.
5 XTK
XTK is a high-performance signal integrity analysis tool developed by Viewlogic in the field of HSSD (High Speed ​​System Design) for high-speed system design. It can accurately analyze the signal quality and transmission line of complex PCB, MCM and multi-PCB board systems. Delay. XTK is a crosstalk analysis toolkit that includes a variety of analysis tools.
6 LineSim and BoardSim
LineSim and BoardSim are simulation tools developed by HyperLynx, a subsidiary of PADS Software. LineSim is used to constrain wiring and layer parameters, set clock routing topologies, select component speeds, diagnose and avoid signal integrity, electromagnetic emissions, and crosstalk before wiring design. BoardSim is used to quickly analyze signal integrity, electromagnetic compatibility, and crosstalk issues in designs, generate crosstalk strength reports, and resolve and resolve crosstalk issues.
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