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Abstract: A CMOS charge pump circuit for charge pump phase-locked loop is designed. In the circuit, three pairs of self-biased high-swing cascode current mirrors are used to mirror the pump current, which increases the output resistance of the charge pump at low voltage, and achieves matching between the upper and lower charge pumps. In order to eliminate the charge sharing problem of the single-ended charge pump, a half-differential current switch structure with bandwidth amplitude voltage following is introduced to improve the performance of the charge pump. The design uses a 0.18μm standard CMOS process. The circuit simulation results show that the pump current matching accuracy is 0.9% in the range of 0.35 to 1.3 V, and the circuit operating frequency is 250 MHz.
Key words: charge pump; phase-locked loop; self-biased cascode current mirror; voltage follow

CMOS Charge Pump Phase-Locked Loop (CPPLL) has the advantages of high speed, low power consumption, low jitter, low cost, etc., and is widely used in circuits such as frequency synthesis and clock recovery. As a key module in the charge pump phase-locked loop, when the charge pump is implemented in the circuit, there are often non-ideal effects such as switching delay, charge and discharge current mismatch, charge injection and charge sharing. For the design of high-performance phase-locked loop, the phase noise and spurious should be minimized, the output current is smoother, the output voltage harmonic component is lower, and the switching delay is reduced. A charge pump circuit with high output impedance and high charge-discharge current matching ratio based on pseudo-differential structure is proposed.

1 Charge Pump Design Analysis The main function of the charge pump is to convert the output signal of the phase frequency detector (PFD) up and down into an analog continuously varying voltage signal for controlling the oscillation frequency of the voltage controlled oscillator (VCO). When the up output signal of the PFD is active, the current source of the charge pump charges the loop filter, the voltage of the voltage control terminal of the VCO rises, and the oscillation frequency of the VCO changes accordingly. Conversely, the down signal causes the charge pump current sink to discharge the loop filter, and the VCO's voltage-controlled voltage signal decreases. When the VCO oscillation frequency and phase are the same as the reference signal, the output signal of the charge pump should be kept at a constant value. However, the traditional charge pump, as shown in Figure 1, has a variety of non-ideal effects, such as charge leakage, charge and discharge current mismatch, charge sharing, pump switching delay, and so on. A good charge pump design should strive to bring the above down to the design specifications.

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