As the system requires a transmission distance greater than 8m, a balanced cable is required. For both ends of the LVDS interface, you can use ASIC and FPGA in two ways. Since Xilinx's Virtex-II series FPGAs directly support the LVDS level standard, this system uses the XC2V250, which not only saves dedicated LVDS level-shifting chips, saves cost, but also integrates other control logic in the system into a single FPGA chip, thereby reducing the difficulty of PCB design, improve the system's integration and reliability. In addition, the transceiver interface logic uses an FPGA, which can be used to reconfigure the transmission direction as needed to dynamically change the number of transceiver channels, which greatly enhances the system's reconfigurability.
The entire data transmission system block diagram is shown in Figure 1. Since data transmission is bi-directional, both the signal processing board and the PCI board have a parallel/serial conversion transmission module and a serial/parallel conversion reception module (both implemented in the FPGA), and the two board cards are connected by balanced cables. In addition, on the signal processing board, the DSP processor sends the write data in the buffer area to the FPGA through the external bus, and the FPGA completes the data exchange with the DSP memory space through the host port of the DSP. On the PCI board, the FPGA exchanges data with the host through the PCI controller. The working principle of the system can be expressed as follows: The DSP processor outputs the processing result to the FPGA buffer memory through the external bus, and completes the parallel/serial conversion of the data in the FPGA, and sends it out through the LVDS serial interface. Data is transmitted to the host receiver card via a balanced cable. In the host computer receiving card, the data is serial/parallel converted and sent to the PCI interface control circuit. The process of outputting data from the upper computer to the DSP processing board is the opposite. Since the system requires the data transmission uplink data rate is less than the downlink data rate, the number of uplink data transmission channels in the design is 1, and the number of downlink data channels is 4. In the case of a transmission distance greater than 8 m, the actual single-channel data transmission rate reaches 264 Mbps.
LVDS Parallel/String Conversion Implementation
Since the FPGA obtains data through the external bus of the DSP processor, its data format is parallel, so it should be converted into a serial bit stream before transmission. Figure 2 shows the block diagram of the HSTX module that implements the parallel/serial conversion and serial transmission functions within the FPGA.
As can be seen from Figure 2, the module has 3 input signals. The clock input CLK, the frame synchronization signal TFR, and the parallel data TCH1 [7:0], respectively. Among them, the CLK frequency is 33MHz, and after the digital clock manager (DCM) phase-locked frequency multiplication, the serial module internal clock CLK1X (33MHz), CLK4XR (33×4=132MHz) and CLK4XF (33×4=132MHz) are obtained. CLK4XR is inverted with CLK4XF and is in phase with CLK1X. The output is three sets of differential signals, which are serial data TCH1[P:N], serial clock TCLK[P:N] and serial frame synchronization signal TFR[P:N]. The rising edge of the input clock CLK signal is valid. When the clock rises, if the frame synchronization signal is high, the input data TCH1[7:O] is latched, and transmission is started one clock cycle later. The output transmit clock TCLK[P:N] is 132MHz and both edges are valid. The output serial data is in a small terminal mode with the data LSB first, and the frame synchronization signal TFR[P:N] outputs a bit sequence 11110000 for synchronization at the receiving end.
As shown in Figure 2, the serial transmission module consists of four modules: LOAD_GEN, OUT_DATA, OUT_FR, and OUT_CLK. The LOAD_GEN module is used to generate the strobe of the loaded data during the parallel/serial conversion. The OUT_DATA module uses shift registers to implement data/serial conversion. The OUT_FR and OUT_CLK blocks are used to generate serial frame synchronization signals and serial clock signals, respectively. These modules are all designed using hardware description language VHDL.
LVDS transmission circuit design
Since the LVDS bus has a transmission rate of 264 Mbps, the requirements for PCB layout and the like are particularly high. In this paper, HyperLynx from Mentor Graphics Inc., a high-speed circuit simulation analysis tool, was used to simulate the LVDS transmission circuit, including transmission line impedance design, termination matching and differential signal wiring. At the same time, the influence of the choice of connectors and transmission cables on the data transmission is considered.
The voltage swing of the LVDS signal is only 350mV, which is a current-driven differential signal operation mode. The longest transmission distance can reach 10m or more. In order to ensure that the signal is propagated in the transmission line, it is not affected by the reflected signal. The LVDS signal requires the transmission line impedance to be controlled and the differential impedance to be 100. In this system application, high-speed circuit simulation analysis tools are used to adjust the line width and line spacing of the traces by properly setting the stack thickness and dielectric parameters, and the single-wire and differential impedance results are calculated to achieve the purpose of impedance control.
The topology of LVDS signals can be point-to-point unidirectional, point-to-point bidirectional or multi-drop. No matter what kind of application, it is necessary to perform termination matching at the receiving end. The matching impedance is equal to the differential impedance, typically 100. The matching resistor is mainly used to absorb the reflected signal of the load. Therefore, it is required to be as close as possible to the receiving end. In this system, the FPGA internal control impedance (Digitally Controlled LED Impedance) is used to directly configure the internal termination impedance of the FPGA to implement termination matching within the FPGA. This not only makes it easy to modify the size of the termination impedance, it makes the termination resistors well matched, and the termination resistance is very close to the receiving end.
The wiring of differential signals is a difficult point in the design of the entire transmission circuit. In general, LVDS signal quality can be ensured by performing differential signal routing in accordance with impedance design rules. In the actual wiring, LVDS differential signal wiring should follow the following principles:
1. The differential pair should be as short as possible, take a straight line, and reduce the number of vias in the wiring. The distance between the signal lines in the differential pair must be consistent to prevent the differential pairs from being routed too long and with too many turns.
2. Between the differential pair and the differential pair should be guaranteed more than 10 times the differential pair spacing, reducing crosstalk between lines. If necessary, place isolated ground vias between differential pairs.
3. LVDS differential signals cannot be split across planes. Although the two differential signals are recirculating paths to each other, cross-division does not cut off the reflow of the signal, but the impedance discontinuity is caused by the lack of a reference plane.
4, try to avoid using the differential signal between layers. In the actual processing of the PCB, the accuracy of laminating between the laminations is much lower than that of etching in the same layer, and the loss of medium in the laminating process, the differential signal between layers cannot guarantee that the interval between the differential lines is equal to the thickness of the dielectric. Therefore, the differential impedance of the differential between layers will change. Therefore, it is recommended to use differentials within the same layer as much as possible.
5. When designing the impedance, try to design a close-coupled mode. That is, the differential pair spacing is less than or equal to the line width.
In addition, high-speed connectors suitable for differential signals should be selected in the LVDS transmission circuit design. On the one hand, the characteristic parameters of the connector can be matched with the LVDS signal impedance, and the signal distortion through the connector is small; on the other hand, it can provide enough Cabling space, design PCB trace width and spacing. For example, AMP's Z-PACK HS3 series connectors are more suitable for high-speed LVDS signal interconnection in terms of electrical performance.
The system uses balanced cables for long-distance transmission. However, traditional cables cannot be used for LVDS data transmission due to LVDS special impedance matching requirements and extremely low timing bias requirements. Trial confirmed that the best performance of twisted pair cable. CAT3 Balanced Twisted Pair cable works best when applied over short distances (approximately 0.5m). Above 0.5m and a data rate greater than 500MHz, the CAT5 balanced cable works best.
Conclusion
The high-speed data transmission system implemented in this paper has been successfully applied to the data transmission between a radar signal processor and the host computer. The transmission distance is greater than 8m, the data transmission rate of a single channel reaches 264Mbps, and the transmission rate of five data channels reaches a total of 1.32GbpS. The transmission process is stable.
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